View ICS849S625I_8628743.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet ics849s625byi revision a october 1, 2012 1 ?2012 integrated device technology, inc. crystal-to-lvpecl/lvds clock synthesizer ICS849S625I 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 xtal_in xtal_out v ee selc0 selc1 oea v cc oeb oec selb0 selb1 v ee qa1 nqa1 qa2 nqa2 v cco v ee qa3 nqa3 qa4 nqa4 qa5 nqa5 v cco nqc1 qc1 nqc0 qc0 nc v cco nqb1 qb1 nqb0 qb0 v cco ref_clk v ee bypass mr sel_ou t sela0 sela1 v cca qa0 nqa0 v cco v cc 48 47 46 45 44 43 42 41 40 39 38 37 general description the ICS849S625I is a high frequency clock generator. the ICS849S625I uses an external 25mhz crystal to synthesize 625mhz, 312.5mhz, 156.25mhz and 125mhz clocks. the ICS849S625I has excellent cycle -to-cycle and rms phase jitter performance. the ICS849S625I operates at full 3. 3v supply mode and is available in a fully rohs compliant 48-lead tqfp, e-pad package. features ? ten selectable differentia l lvpecl or lvds outputs ? output frequencies of 625m hz, 312.5mhz, 156.25mhz or 125mhz using a 25mhz crystal. ? crystal interface designed for a 25mhz, parallel resonant crystal ? cycle-to-cycle jitter: 25ps (maximum) ? rms phase jitter at 156.25mhz (1mhz - 20mhz): 0.375ps (typical), lvds outputs ? output duty cycle: 53% (maximum) ? full 3.3v supply mode ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) packaging frequency table for bank a, b and c outputs crystal frequency (mhz) m feedback divider vco freq uency (mhz) nx output divider output frequency (mhz) 25 25 625 1 625 25 25 625 2 312.5 25 25 625 4 156.25 25 25 625 5 125 48 lead tqfp, e-pad 7mm x 7mm x 1.0mm package body y package top view pin assignment ICS849S625I
ics849s625byi revision a october 1, 2012 2 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer block diagram phase detector vco 575mhz - 630mhz m = 25 2 2 2 2 2 6 6 osc mr bypass sel_out ref_clk xtal_in xtal_out nqa[0:5] nqb[0:1] qb[0:1] qa[0:5] qc[0:1] nqc[0:1] oea pullup oeb pullup sela[1:0] selb[0:1] selc[0:1] 25mhz oec pullup pulldown pulldown pulldown pulldown pulldown pulldown pulldown na = 1, 2, 4, 5 nc = 1, 2, 4, 5 nb = 1, 2, 4, 5 2 2 2 1 0
ics849s625byi revision a october 1, 2012 3 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer table 1. pin descriptions note: pullup and pulludown refer to internal input resistors. see table 2, pin characteristics, for typical values. number name type description 1, 2 xtal_in xtal_out input crystal oscillator interface. xtal_in is the input, xtal_out is the output. 3, 12, 31, 46 v ee power negative supply pins. 4, 5 selc0, selc1 input pulldown selects the output divider value. see table 3d. lvcmos/lvttl interface levels. 6oeainputpullup active high output enable. when logic high, bank a outputs are enabled and active. when logic low, the outputs ar e disabled and forced to high/low. lvcmos/lvttl interface levels. 7, 48 v cc power core supply pins. 8oebinputpullup active high output enable. when logic high, bank b outputs are enabled and active. when logic low, the outputs ar e disabled and forced to high/low. lvcmos/lvttl interface levels. 9oecinputpullup active high output enable. when logic high, bank c outputs are enabled and active. when logic low, the outputs ar e disabled and forced to high/low. lvcmos/lvttl interface levels. 10, 11 selb0, selb1 input pulldown selects the output divider value. see table 3c. lvcmos/lvttl interface levels. 13, 19, 24, 32, 37 v cco power output supply pins. 14, 15 nqc1, qc1 output different ial output pair. lvpecl or lvds interface levels. 16, 17 nqc0, qc0 output different ial output pair. lvpecl or lvds interface levels. 18 nc unused no connect. 20, 21 nqb1, qb1 output different ial output pair. lvpecl or lvds interface levels. 22, 23 nqb0, qb0 output different ial output pair. lvpecl or lvds interface levels. 25, 26 nqa5, qa5 output different ial output pair. lvpecl or lvds interface levels. 27, 28 nqa4, qa4 output different ial output pair. lvpecl or lvds interface levels. 29, 30 nqa3, qa3 output different ial output pair. lvpecl or lvds interface levels. 33, 34 nqa2, qa2 output different ial output pair. lvpecl or lvds interface levels. 35, 36 nqa1, qa1 output different ial output pair. lvpecl or lvds interface levels. 38, 39 nqa0, qa0 output different ial output pair. lvpecl or lvds interface levels. 40 v cca power analog supply pin. 41, 42 sela1, sela0 input pulldown selects the output divider value. see table 3b. lvcmos/lvttl interface levels. 43 sel_out input pulldown selects between either lvds or lv pecl output levels. see table 3a. lvcmos/lvttl interface levels. 44 mr input pulldown master reset. lvcmos/lvttl interface levels. 45 bypass input pulldown pll bypass mode select pin. see table 3f. lvcmos/lvttl interface levels. 47 ref_clk input pulldown single-ended reference clock input. lvcmos/lvttl interface levels.
ics849s625byi revision a october 1, 2012 4 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer table 2. pin characteristics function tables table 3a. sel_out function table table 3e. mr function table table 3b. sela function table table 3f. bypass function table table 3c. selb function table table 3d. selc function table symbol parameter test conditio ns minimum typical maximum units c in input capacitance 2 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? input output levels sel_out 0 (default) lvds 1 lvpecl input device function mr 0 (default) normal 1master reset inputs na bank a output divider sela0 sela1 0 (default) 0 (default) 1 01 2 10 4 11 5 input device function bypass 0 (default) pll mode. the output frequency is the vco frequency divided by the selected output divider. 1 bypass mode. the output frequency is the ref_clk frequency divided by two and then divided by the selected output divider. inputs nb bank b output divider selb0 selb1 0 (default) 0 (default) 1 01 2 10 4 11 5 inputs nc bank c output divider selc0 selc1 0 (default) 0 (default) 1 01 2 10 4 11 5
ics849s625byi revision a october 1, 2012 5 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. lvds power supply dc characteristics, v cc = v cco = 3.3v 5%, t a = -40c to 85c note: outputs configured as lvds (sel_out = 0). note: for the power supply voltage sequence inform ation, see applications information section. table 4b. lvpecl power supply dc characteristics, v cc = v cco = 3.3v 5%, v ee = 0v, t a = -40c to 85c note: outputs configured as lvpecl (sel_out = 1). note: for the power supply voltage sequence inform ation, see applications information section. item rating supply voltage, v cc 4.6v inputs, v i xtal_in other inputs 0v to v cc -0.5v to v cc + 0.5v outputs, lvpecl i o continuos current surge current outputs, lvds i o continuos current surge current 50ma 100ma 10ma 15ma package thermal impedance, ? ja 33.1 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage v cc ? 0.16 3.3 v cc v v cco output supply voltage 3.135 3.3 3.465 v i cc power supply current 107 ma i cca analog supply current 16 ma i cco output supply current 228 ma symbol parameter test conditio ns minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage v cc ? 0.16 3.3 v cc v v cco output supply voltage 3.135 3.3 3.465 v i ee power supply current 181 ma i cca analog supply current 16 ma
ics849s625byi revision a october 1, 2012 6 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer table 4c. lvcmos/lvttl dc characteristics, v cc = v cco = 3.3v 5%, v ee = 0v, t a = -40c to 85c table 4d. lvpecl dc characteristics, v cc = v cco = 3.3v 5%, v ee = 0v, t a = -40c to 85c table 4e. lvds dc characteristics, v cc = v cco = 3.3v 5%, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v cc = 3.3v 2.2 v cc + 0.3 v v il input low voltage v cc = 3.3v -0.3 0.8 v i ih input high current ref_clk, bypass, mr, sela[1:0], selb[1:0], selc[1:0], sel_out v cc = v in = 3.465v 150 a oea, oeb, oec v cc = v in = 3.465v 10 a i il input low current ref_clk, bypass, mr, sela[1:0], selb[1:0], selc[1:0], sel_out v cc = 3.465v, v in = 0v -10 a oea, oeb, oec v cc = 3.465v, v in = 0v -150 a symbol parameter test conditio ns minimum typical maximum units v oh output high voltage v cco ? 1.2 v cco ? 0.7 v v ol output low voltage v cco ? 2.0 v cco ? 1.5 v v swing peak-to-peak output voltage swing 0.6 1.0 v symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 268 475 mv ? v od v od magnitude change 50 mv v os offset voltage 1.125 1.375 v ? v os v os magnitude change 50 mv
ics849s625byi revision a october 1, 2012 7 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer ac electrical characteristics table 5a. lvpecl ac characteristics, v cc = v cco = 3.3v 5%, v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: outputs configured as lvpecl (sel_out = 1). note 1: refer to the phase noise plot. note 2: this parameter is defined in accordance with jedec standard 65. table 5b. lvds ac characteristics, v cc = v cco = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: outputs configured as lvds (sel_out = 0). note 1: refer to the phase noise plot. note 2: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditio ns minimum typical maximum units f out output frequency qx = 1 575 625 630 mhz qx = 2 287.5 312.5 315 mhz qx = 4 143.75 156.25 157.5 mhz qx = 5 115 125 126 mhz t jit(?) rms phase jitter (random); note 1 156.25mhz, integration range: (1mhz ? 20mhz) 0.373 0.422 ps 156.25mhz, integration range: (12khz ? 20mhz) 0.694 1.04 ps t jit(cc) cycle-to-cycle jitter; note 2 25 ps t r / t f output rise/fall time 10% to 90% 65 180 350 ps odc output duty cycle 47 53 % t lock pll lock time 130 ms symbol parameter test conditio ns minimum typical maximum units f out output frequency qx = 1 575 625 630 mhz qx = 2 287.5 312.5 315 mhz qx = 4 143.75 156.25 157.5 mhz qx = 5 115 125 126 mhz t jit(?) rms phase jitter (random); note 1 156.25mhz, integration range: (1mhz ? 20mhz) 0.375 0.413 ps 156.25mhz, integration range: (12khz ? 20mhz) 0.712 1.26 ps t jit(cc) cycle-to-cycle jitter; note 2 20 ps t r / t f output rise/fall time 10% to 90% 65 190 350 ps odc output duty cycle 47 53 % t lock pll lock time 130 ms
ics849s625byi revision a october 1, 2012 8 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer typical phase noise at 156.25mhz (lvpecl) typical phase noise at 156.25mhz (lvpecl) 156.25mhz rms phase jitter (random) 1mhz to 20mhz = 0.373ps (typical) noise power dbc hz offset frequency (hz) noise power dbc hz 156.25mhz rms phase jitter (random) 12khz to 20mhz = 0.694ps (typical) offset frequency (hz)
ics849s625byi revision a october 1, 2012 9 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer typical phase noise at 156.25mhz (lvds) typical phase noise at 156.25mhz (lvds) noise power dbc hz 156.25mhz rms phase jitter (random) 1mhz to 20mhz = 0.375ps (typical) offset frequency (hz) noise power dbc hz 156.25mhz rms phase jitter (random) 12khz to 20mhz = 0.712ps (typical) offset frequency (hz)
ics849s625byi revision a october 1, 2012 10 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer parameter measureme nt information lvpecl output load ac test circuit rms phase jitter lvpecl output rise/fall time lvds output load ac test circuit cycle-to-cycle jitter lvds output rise/fall time scope qx nqx v ee v cc, v cca 2v -1.3v0.165v v cco 2v offset frequency f 1 f 2 phase noise plot area under curve defined by the offset frequency markers rms phase jitter = noise power 2 * * ? 1 * 10% 90% 90% 10% t r t f v swing nqax, nqbx, nqcx qax, qbx, qcx scope qx nqx 3.3v5% power supply +? float gnd v cc, v cco v cca ? ? ? ? t cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles nqax, nqbx, nqcx qax, qbx, qcx 10% 90% 90% 10% t r t f v od nqax, nqbx, nqcx qax, qbx, qcx
ics849s625byi revision a october 1, 2012 11 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer parameter measurement in formation, continued output duty cycle/pulse width/period differential output voltage setup offset voltage setup nqax, nqbx, nqcx t pw t period t pw t period odc = x 100% qax, qbx, qcx 100 out out dc input v dd lvds out out lvds dc input ? v os / v os v dd
ics849s625byi revision a october 1, 2012 12 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer applications information recommendations for unused input and output pins inputs: ref_clk input for applications not requiring the use of the reference clock, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the ref_clk to ground. crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs all unused lvpecl outputs can be le ft floating. we recommend that there is no trace attached. both si des of the differential output pair should either be left floating or terminated. lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached. table 6. recommended crystal specifications note: external tuning capacitors must be used for proper operation. power supply voltage sequence information no power sequence restrictions apply if v cc and v cca are supplied by the same power plane and the recommended v cca filter is used ( see figure 6). v cco may be applied at any time before or after v cc and v cca are applied. if v cc and v cca are not supplied by the same power plane, v cca must be powered on before or at the same time v cc is applied. the v cco supply voltage may be applied at any time. symbol parameter value crystal cut fundamental at cut resonance parallel resonance f t frequency tolerance 25ppm at 25 0 c f s frequency stability 25ppm over -40 0 c to +85 0 c c l load capacitance 18pf c o shunt capacitance 5pf - 7pf esr equivalent series resistance 20 ? - 50 ? aging @ 25 0 c 15ppm/10 years maximum
ics849s625byi revision a october 1, 2012 13 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer overdriving the xtal interface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 1a. the xtal_out pin can be left floating. the maximum amplitude of the input signal should not exceed 2v and the input edge rate can be as slow as 10ns. this configuration requires that the output impedance of t he driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . by overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. figure 1a. general diagram for lvcmos driver to xtal input interface figure 1b. general diagram for lvpec l driver to xtal input interface r2 100 r1 100 rs 43 ro ~ 7 ohm driv er_lvcmos zo = 50 ohm c1 0.1uf 3.3v 3.3v cry stal input interf ace xta l _ i n xta l _ o u t cry stal input interf ace xtal_in xtal_out r3 50 c1 0.1uf r2 50 r1 50 zo = 50 ohm lvpecl zo = 50 ohm vcc=3.3v
ics849s625byi revision a october 1, 2012 14 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer lvds driver termination a general lvds interface is shown in figure 2. standard termination for lvds type output stru cture requires both a 100 ? parallel resistor at the receiver and a 100 ? differential transmission line environment. in order to avoid any transmission line reflection issues, the 100 ? resistor must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 2 can be used with either type of output structure. if using a non-standard termination, it is recommended to contact idt and conf irm if the output is a current source or a voltage source type structure. in addition, since these outputs are lvds compatible, the input receivers amplitude and common mode input range should be verified for compatibility with the output. figure 2. typical lvds driver termination termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are lo w impedance follower outputs that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 3a. 3.3v lvpecl output termination figure 3b. 3.3v lvpecl output termination 100 ? + 100 differential transmission line lvds driver lvds receiver 3.3v v cc - 2v r1 50 r2 50 rtt z o = 50 z o = 50 + _ rtt = * z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v lvpecl input r1 84 r2 84 3.3v r3 125 r4 125 z o = 50 z o = 50 lvpecl input 3.3v 3.3v + _
ics849s625byi revision a october 1, 2012 15 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 4. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/electrically enhance leadframe base package, amkor technology. figure 4. assembly for exposed pad thermal rel ease path - side view (drawing not to scale) ground plane land pattern solder thermal via exposed heat slug (ground pad) pin pin pad solder pin pin pad solder
ics849s625byi revision a october 1, 2012 16 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer application schematic example figure 5 shows an example of ICS849S625I application schematic . in this example, the device is operated at v cc = v cca = v cco = 3.3v. an 18pf parallel resonant 25mhz crystal is used . the load capacitance c1 = 27pf and c2 = 27pf are recommended for frequency accura cy. depending on the parasitics of the printed circuit board layout, these values mi ght required slight adjustment to optimize the frequency accuracy. crystals with other load capacitance specifications can be used. this will r equire adjusting c1 and c2. for this devi ce, the crystal load capacitors are requ ired for proper operation. as with any high speed analog circuitry, the power supply pins are vulnerable to noise. to achieve optimum jitter performance, power supply isolation is required. the ICS849S625I provides separate po wer supplies to isolate from coupling into the internal pll. in order to achieve the best possible filterin g, it is recommended that the placement of the filter components be on the device side of the pcb as close to the power pins as possible. if space is limited, the 0. 1uf capacitor in each power pin filter should be placed on t he device side of the pcb and the other components can be placed on the opposite side. power supply filter recommendations are a ge neral guideline to be used for reducing external noise from coupling into the devic es. the filter performance is designed for wide range of noise frequencies. this low-pass filter starts to atte nuate noise at approximately 10 khz. if a specific frequency noise component is known, such as switching power suppl y frequencies, it is recommended that component values be adju sted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability sugge sts adding bulk capacitances in the local area of all devices. the schematic example focuses on functional connections and is not configuration specific. refer to the pin description and fun ctional tables in the datasheet to ensure the l ogic control inputs are properly set. figure 5. ICS849S625I application schematic ? 3. 3v selc1 selc0 selb0 sela1 sela0 vcca oec selb1 oeb oea pll_by pass nreset sel_out nqa qa0 nqa4 qa4 nqa3 qa3 nqa2 qa2 nqa1 qa1 nqc1 qc1 nqb1 qb1 nqa5 qa5 qb0 nqc0 qc0 nqb0 vcc vc co rd2 1k zo_dif f = 100 ohm r4 133 blm18bb221sn 1 ferrite bead 1 2 zo = 50 ohm ru2 n ot install c10 0. 01u r7 1k r9 50 rd1 not install r10 50 blm18bb221sn 2 ferrite bead 1 2 zo = 50 ohm c4 0.01u r2 10 c1 27pf c13 10uf c17 0.1uf r6 82.5 c2 0. 01u c3 0.01u + - + - c5 0. 01u zo = 50 ohm r1 100 x1 25mhz c2 27pf + - r8 50 zo = 50 ohm c15 0. 1uf r3 133 c1 0.01u c12 0. 1uf ru1 1k c14 0.1uf r5 82.5 c7 0.01u u1 i cs849s625i xtal_in 1 xtal_ou t 2 sela0 41 sela1 42 selb0 10 selb1 11 selc0 4 selc1 5 oea 6 oeb 8 oec 9 nc 18 qa0 39 nqa0 38 qa1 36 nqa1 35 qa2 34 nqa2 33 qa3 30 nqa3 29 qa4 28 nqa4 27 qa5 26 nqa5 25 qb0 23 nqb0 22 qb1 21 nqb1 20 qc 0 17 nqc 0 16 qc 1 15 nqc 1 14 vcca 40 vcco 13 vcco 19 vc co 24 vcco 32 vcco 37 vcc 7 vcc 48 vee 3 vee 12 vee 31 vee 46 sel_out 43 mr 44 bypass 45 ref _clk 47 c6 0.01u c11 10uf c16 10uf vcco vcc vc c vcc vcc 3.3v lvds term ination 3.3v lvpecl opti onal y-term in ati on set logi c input to '1' set logic input to '0' to logic input pins logic control input examples to logic input pins cl =1 8p f lvpecl te rmi na tio n tuning capacitor required
ics849s625byi revision a october 1, 2012 17 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer lvpecl power considerations this section provides information on power dissipa tion and junction temperature for the ICS849S625I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS849S625I is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. the maximum current at 85c is as follows: i ee_max = 170ma ? power (core) max = v cc_max * i ee_max = 3.465v * 170ma = 589.05mw ? power (outputs) max = 33.2mw/loaded output pair if all outputs are loaded, the total power is 10 * 33.2mw = 332mw total power_ max (3.465v, with all outputs s witching) = 589.05mw + 332mw = 921.05mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 33.1c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.921w * 33.1c/w = 115.5c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ? ja for 48 lead tqfp, e-pad, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 33.1c/w 27.2c/w 25.7c/w
ics849s625byi revision a october 1, 2012 18 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pair. lvpecl output driver circuit and termination are shown in figure 6. figure 6. lvpecl driver circuit and termination t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cco ? 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.7v (v cco_max ? v oh_max ) = 0.7v ? for logic low, v out = v ol_max = v cco_max ? 1.5v (v cco_max ? v ol_max ) = 1.5v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v oh_max ) = [(2v ? (v cco_max ? v oh_max ))/r l ] * (v cco_max ? v oh_max ) = [(2v ? 0.7v)/50 ? ] * 0.7v = 18.2mw pd_l = [(v ol_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v ol_max ) = [(2v ? (v cco_max ? v ol_max ))/r l] * (v cco_max ? v ol_max ) = [(2v ? 1.5v)/50 ? ] * 1.5v = 15mw total power dissipation per output pair = pd_h + pd_l = 33.2mw v out v cco v cco - 2v q1 rl 50
ics849s625byi revision a october 1, 2012 19 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer lvds power considerations this section provides information on power dissipa tion and junction temperature for the ICS849S625I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics849s6 25i is the sum of the core power plus th e analog power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. the maximum current at 85c is as follows: i cc_max = 100ma i cca_max = 15ma i cco_max = 212ma ? power (core) max = v cc_max * (i cc_max + i cca_max ) = 3.465v * (100ma + 15ma) = 398.475mw ? power (outputs) max = v cco_max * i cco_max = 3.465v * 212ma = 734.58mw total power_ max = 398.475mw + 734.58mw = 1133.1mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 33.1c/w per table 8 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 1.133w * 33.1c/w = 122.5c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 8. thermal resistance ? ja for 48 lead tqfp, e-pad, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 33.1c/w 27.2c/w 25.7c/w
ics849s625byi revision a october 1, 2012 20 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer reliability information table 9. ? ja vs. air flow table for a 48 lead tqfp, e-pad transistor count the transistor count for ICS849S625I is: 3696 ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 33.1c/w 27.2c/w 25.7c/w
ics849s625byi revision a october 1, 2012 21 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer package outline and package dimensions package outline - y suffix for 48 lead tqfp, e-pad table 10. package dimensions for 48 lead tqfp, e-pad reference document: jedec publication 95, ms-026 jedec variation: bbc - hd all dimensions in millimeters symbol minimum nominal maximum n 48 a 1.20 a1 0.05 0.10 0.15 a2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 0.20 d & e 9.00 basic d1 & e1 7.00 basic d2 & e2 5.50 ref. d3 & e3 3.5 e 0.5 basic l 0.45 0.60 0.75 ? 0 7 -hd version exposed pad down -tab, exposed part of connection bar or tie bar 0.20 tab
ics849s625byi revision a october 1, 2012 22 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer ordering information table 11. ordering information part/order number marking package shipping packaging temperature 849s625byilf ics49s625bil ?lead-free? 48 lead tqfp, e-pad tray -40 ? c to 85 ? c 849s625byilft ics49s625bil ?lead-free? 48 lead tqfp, e-pad tape & reel -40 ? c to 85 ? c
ics849s625byi revision a october 1, 2012 23 ?2012 integrated device technology, inc. ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer revision history sheet rev table page description of change date a t4e 6 vod: changed units from v to mv 10/1/12 t11 22 deleted quantity from tape &rreel. deleted lead-free note.
ICS849S625I data sheet crystal-to-lvpecl/lvds clock synthesizer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involvi ng extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signif- icantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2012. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

▲Up To Search▲

Price & Availability of ICS849S625I

	To Download ICS849S625I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .